An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a large amount of current is provided to an integrated circuit (IC). The large current may be built-up from a variety of sources, such as the human body. An ESD event commonly results from the discharge of a high voltage potential (typically, several kilovolts) and leads to pulses of high current (several amperes) of a short duration (typically, 100 nanoseconds). An ESD event is generated within an IC, illustratively, by human contact with the leads of the IC or by electrically charged machinery being discharged in other leads of an IC. During installation of integrated circuits into products, these electrostatic discharges may destroy the IC and thus require expensive repairs on the products, which could have been avoided by providing a mechanism for dissipation of the electrostatic discharge to which the IC may have been subjected.
Manufacturers and users of ICs must take precautions to avoid ESD. For example, ESD prevention can be part of the device itself and may include special design techniques for device input and output pins. Additionally, external protection components can also be used with circuit layout. For example, to protect ICs from an ESD event, many schemes have been implemented, including use of a silicon controlled rectifier (SCR). An SCR can sustain high currents, hold the voltage across the SCR at a low level and may be implemented to bypass high current discharges associated with an ESD event.
Recent advances in integrated circuits have included further development of silicon-on-insulator (SOI) technology. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. SOI technology utilizes an insulating substrate in place of a conventional silicon substrate to improve process characteristics, such as speed and latch-up susceptibility. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices.
Devices in advanced microelectronics employ silicon-on-insulator (SOI) technology for improved performance, where the active area of a device is in a thin silicon layer, isolated from the bulk silicon substrate by a buried oxide (BOX) layer. The BOX layer provides electrical isolation from the substrate for improved field distribution in the active area. The implementation of SOI technology is one of several manufacturing strategies employed to allow the continued miniaturization of microelectronic devices.
However, SOI technology is still susceptible to an ESD event. Moreover, due to the thermal conductivity of the insulator, e.g., buried oxide, and the floating body effect from active devices being formed over the insulator instead of a semiconductor substrate, the ESD problem has been especially pronounced in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) field effect technologies, which require new considerations and approaches for ESD protection.
An SCR is used for advanced SOI technologies to provide thin oxide, e.g., SiO2, I/O ESD protection. Additionally, utilizing an SCR, high ESD performance and low capacitance loading may be achieved. Moreover, application specific integrated circuits (ASICs) such as high-speed series link (HSS) applications using advanced SOI technologies has necessitated that SCRs be enabled for SOI. However, an SCR in bulk technologies cannot be directly mapped to SOI technologies.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.